'This changeset was generated by squeaksource, it might need manual editing'!
"Change Set:		VMMaker.oscog-eem.2799(2798)
Date:			2 September 2020
Author:			(generated from MC packages below)

Name: VMMaker.oscog-eem.2799
Author: eem
Time: 2 September 2020, 10:33:06.369398 am
UUID: 80ed3233-a0ed-4818-ad21-8311a85e70f9
Ancestors: VMMaker.oscog-eem.2798

Support for compact ARMv8 (& similar) integer multiply overflow detection.

Simulator breakpoint convenience."!

SharedPool subclass: #CogRTLOpcodes
	instanceVariableNames: ''
	classVariableNames: 'AddCqR AddCqRR AddCwR AddRR AddRRR AddRdRd AddRsRs AddcCqR AddcRR AlignmentNops AndCqR AndCqRR AndCwR AndRR ArithmeticShiftRightCqR ArithmeticShiftRightCqRR ArithmeticShiftRightRR Call CallFull CallR ClzRR CmpC32R CmpCqR CmpCwR CmpRR CmpRdRd CmpRsRs ConvertRRd ConvertRRs ConvertRdR ConvertRdRs ConvertRsR ConvertRsRd DivRdRd DivRsRs Fill32 FirstJump FirstShortJump Jump JumpAbove JumpAboveOrEqual JumpBelow JumpBelowOrEqual JumpCarry JumpFPEqual JumpFPGreater JumpFPGreaterOrEqual JumpFPLess JumpFPLessOrEqual JumpFPNotEqual JumpFPOrdered JumpFPUnordered JumpFull JumpGreater JumpGreaterOrEqual JumpLess JumpLessOrEqual JumpLong JumpLongNonZero JumpLongZero JumpMulOverflow JumpNegative JumpNoCarry JumpNoMulOverflow JumpNoOverflow JumpNonNegative JumpNonZero JumpOverflow JumpR JumpZero Label LastJump LastRTLCode Literal LoadEffectiveAddressMwrR LogicalShiftLeftCqR LogicalShiftLeftCqRR LogicalShiftLeftRR LogicalShiftRightCqR LogicalShiftRightCqRR LogicalShiftRightRR MoveA32R MoveAbR MoveAwR MoveC32R MoveCqR MoveCwR MoveM16rR MoveM32rR MoveM32rRs MoveM64rRd MoveM8rR MoveMbrR MoveMs8rR MoveMwrR MoveRA32 MoveRAb MoveRAw MoveRM16r MoveRM32r MoveRM8r MoveRMbr MoveRMwr MoveRR MoveRRd MoveRX16rR MoveRX32rR MoveRXbrR MoveRXwrR MoveRdM64r MoveRdR MoveRdRd MoveRsM32r MoveRsRs MoveX16rRR MoveX32rRR MoveXbrRR MoveXwrRR MulRdRd MulRsRs NativePopR NativePushR NativeRetN NegateR Nop NotR OrCqR OrCqRR OrCwR OrRR PopR PrefetchAw PushCq PushCw PushR RetN RotateLeftCqR RotateRightCqR SignExtend16RR SignExtend32RR SignExtend8RR SqrtRd SqrtRs Stop SubCqR SubCwR SubRR SubRRR SubRdRd SubRsRs SubbCqR SubbRR TstCqR XorCqR XorCwR XorRR XorRdRd XorRsRs ZeroExtend16RR ZeroExtend32RR ZeroExtend8RR'
	poolDictionaries: ''
	category: 'VMMaker-JIT'!

!CogRTLOpcodes commentStamp: 'eem 12/26/2015 14:00' prior: 0!
I am a pool for the Register-Transfer-Language to which Cog compiles.  I define unique integer values for all RTL opcodes.  See CogAbstractInstruction for instances of instructions with the opcodes that I define.!

!CogRTLOpcodes class methodsFor: 'class initialization' stamp: 'eem 9/2/2020 10:16'!
initialize
	"Abstract opcodes are a compound of a one word operation specifier and zero or more operand type specifiers.
	 The assembler is in Cogit protocol abstract instructions and uses `at&t' syntax, assigning to the register on the
	 right. e.g. MoveRR is the Move opcode with two register operand specifiers and defines a move register to
	 register instruction from operand 0 to operand 1.  The word and register size is assumed to be either 32-bits
	 on a 32-bit architecture or 64-bits on a 64-bit architecture.  The abstract machine is mostly a 2 address machine
	 with the odd three address instruction added to better exploit RISCs.
			(self initialize)
	The operand specifiers are
		R		- general purpose register
		Rs		- single-precision floating-point register
		Rd		- double-precision floating-point register
		Cq		- a `quick' constant that can be encoded in the minimum space possible.
		Cw		- a constant with word size where word is the default operand size for the Smalltalk VM, 32-bits
				  for a 32-bit VM, 64-bits for a 64-bit VM.  The generated constant must occupy the default number
				  of bits.  This allows e.g. a garbage collector to update the value without invalidating the code.
		C32	- a constant with 32 bit size.  The generated constant must occupy 32 bits.
		C64	- a constant with 64 bit size.  The generated constant must occupy 64 bits.
		Aw		- memory word (32-bits for a 32-bit VM, 64-bits for a 64-bit VM) at an absolute address
				  See note about MoveAwR and MoveRAw in the opcodeNames literal array below!!!!
		Ab		- memory byte at an absolute address
		A32	- memory 32-bit halfword at an absolute address
		Mwr	- memory word whose address is at a constant offset from an address in a register
		Mbr		- memory byte whose address is at a constant offset from an address in a register (zero-extended on read)
		M16r	- memory 16-bit halfword whose address is at a constant offset from an address in a register
		M32r	- memory 32-bit halfword whose address is at a constant offset from an address in a register
		M64r	- memory 64-bit doubleword whose address is at a constant offset from an address in a register
		Xbr		- memory byte whose address is r * byte size away from an address in a register
		X16r	- memory 16-bit halfword whose address is r * (2 bytes size) away from an address in a register
		X32r	- memory 32-bit halfword whose address is r * (4 bytes size) away from an address in a register (64-bit ISAs only)
		Xwr		- memory word whose address is r * word size away from an address in a register
		Xowr	- memory word whose address is o + (r * word size) away from an address in a register (scaled indexed)

	An alternative would be to decouple opcodes from operands, e.g.
		Move := 1. Add := 2. Sub := 3...
		RegisterOperand := 1. ConstantQuickOperand := 2. ConstantWordOperand := 3...
	But not all combinations make sense and even fewer are used so we stick with the simple compound approach.

	The assumption is that comparison and arithmetic instructions set condition codes (*) and that move instructions
	leave the condition codes unaffected.  In particular LoadEffectiveAddressMwrR does not set condition codes
	although it can be used to do arithmetic.  On processors such as MIPS this distinction is invalid; there are no
	condition codes.  So the backend is allowed to collapse operation, branch pairs to internal instruction definitions
	(see senders and implementors of noteFollowingConditionalBranch:).
	We also assume that arithmetic sets the carry flag but that Add?R/Sub?R et al ignore the carry flag as a source operand.
	This is because multiple precision arithmetic is implem ented in plugins (LargeIntegerPlugins) and hence not (yet)
	important here.
	(*) the back end is not expected to set the condition codes if arithmetic is done to change the value of the stack pointer.

	Not all of the definitions in opcodeDefinitions below are implemented.  In particular we do not implement the
	XowrR scaled index addressing mode since it requires 4 operands.

	Not all instructions make sense on all architectures.  MoveRRd and MoveRdR are meaningful only on 64-bit machines.

	Note that there are no generic division instructions defined, but a processor may define some.

	Branch/Call ranges.  Jump[Cond] can be generated as short as possible.  Call/Jump[Cond]Long must be generated
	in the same number of bytes irrespective of displacement since their targets may be updated, but they need only
	span 16Mb, the maximum size of the code zone.  This allows e.g. ARM to use single-word call and jump instructions
	for most calls and jumps.  CallFull/JumpFull must also be generated in the same number of bytes irrespective of
	displacement for the same reason, but they must be able to span the full (32-bit or 64-bit) address space because
	they are used to call code in the C runtime, which may be distant from the code zone.  CallFull/JumpFull are allowed
	to use the cResultRegister as a scratch if required (e.g. on x64 where there is no direct 64-bit call or jump).

	Byte reads.  If the concrete compiler class answers true to byteReadsZeroExtend then byte reads must zero-extend
	the byte read into the destination register.  If not, the other bits of the register should be left undisturbed and the
	Cogit will add an instruction to zero the register as required.  Under no circumstances should byte reads sign-extend.

	16-bit (and on 64-bits, 32-bit) reads.  These /are/ expected to always zero-extend.

	Arithmetic operations have as their destination the last operand except Cmp; CmpXR is SubRX with no update of result.
	We only require that CmpR: reg R: SPReg be supported, and do not use CmpR: SPReg R: reg.
	This is in support of ARMv8, which only supports one direction of comparison with the stack pointer.

	By default we use the native stack pointer and in this form PopR PushR and RetN are correspondingly equivalent
	to NativePopR NativePushR and NativeRetN, and SPReg = NativeSPReg.  But if the backEnd answers false to
	usesNativeSPReg then NativePopR, NativePushR, and NativeRetN operate on the NativeSPReg, PopR PushR and
	RetN operate on SPReg, and NativeSPReg ~= SPReg."

	| opcodeNames refs |
	opcodeNames := #("Noops & Pseudo Ops"
						Label
						Literal			"a word-sized literal"
						AlignmentNops
						Fill32			"output four byte's worth of bytes with operand 0"
						Nop

						"Control"
						Call					"call within the code zone"
						CallFull				"call anywhere within the full address space"
						CallR
						RetN
						JumpR				"Not a regular jump, i.e. not pc dependent."
						Stop				"Halt the processor"

						"N.B.  Jumps are contiguous.  Long and Full jumps are contiguous within them.  See FirstJump et al below"
						JumpFull				"Jump anywhere within the address space"
						JumpLong				"Jump anywhere within the 16mb code zone."
						JumpLongZero			"a.k.a. JumpLongEqual"
						JumpLongNonZero		"a.k.a. JumpLongNotEqual"
						Jump					"short jumps; can be encoded in as few bytes as possible; will not be disturbed by GC or relocation."
						JumpZero				"a.k.a. JumpEqual"
						JumpNonZero			"a.k.a. JumpNotEqual"
						JumpNegative
						JumpNonNegative
						JumpOverflow
						JumpNoOverflow
						JumpMulOverflow 		"Only on processors that lack integer multiply overflow detection, e.g. ARMv8"
						JumpNoMulOverflow 	"Defined here so that CogAbstractInstruction>>isJump is a single range comparison."
						JumpCarry
						JumpNoCarry
						JumpLess				"signed"
						JumpGreaterOrEqual
						JumpGreater
						JumpLessOrEqual
						JumpBelow				"unsigned"
						JumpAboveOrEqual
						JumpAbove
						JumpBelowOrEqual

						JumpFPEqual
						JumpFPNotEqual
						JumpFPLess
						JumpFPLessOrEqual
						JumpFPGreater
						JumpFPGreaterOrEqual
						JumpFPOrdered
						JumpFPUnordered

						"Data Movement; destination is always last operand"
						MoveRR
						"N.B. On certain targets (including X64) MoveAwR & MoveRAw may
						 smash TempReg if the register argument is either FPReg or SPReg!!!!"
						MoveAwR MoveA32R
						MoveRAw MoveRA32
						MoveAbR
						MoveRAb
						MoveMwrR MoveRMwr MoveXwrRR MoveRXwrR "MoveXowrR MoveRXowr""Unused"
						MoveM8rR MoveMs8rR MoveRM8r 
						MoveM16rR MoveRM16r MoveX16rRR MoveRX16rR
						MoveM32rR MoveRM32r MoveX32rRR MoveRX32rR
						MoveMbrR MoveRMbr MoveXbrRR MoveRXbrR
						MoveCqR MoveCwR MoveC32R "MoveC64R""Not used"
						MoveRRd MoveRdR MoveRdRd MoveM64rRd MoveRdM64r
						MoveRsRs MoveM32rRs MoveRsM32r
						PopR PushR PushCq PushCw
						NativePopR NativePushR NativeRetN
						PrefetchAw

						"Arithmetic; destination is always last operand except Cmp; CmpXR is SubRX with no update of result"
						"We only require that CmpR: reg R: SPReg be supported, and do not use CmpR: SPReg R: reg.
						 This is in support of ARMv8, which only supports one direction of comparison with the stack pointer."
						LoadEffectiveAddressMwrR "LoadEffectiveAddressXowrR" "Variants of add/multiply"
						NegateR "2's complement negation"
						NotR
						ArithmeticShiftRightCqR ArithmeticShiftRightRR
						LogicalShiftRightCqR LogicalShiftRightRR
						LogicalShiftLeftCqR LogicalShiftLeftRR
						RotateLeftCqR RotateRightCqR

						CmpRR AddRR SubRR AndRR OrRR XorRR
						CmpCqR AddCqR SubCqR AndCqR OrCqR TstCqR XorCqR
						CmpCwR CmpC32R AddCwR SubCwR AndCwR OrCwR XorCwR
						AddcRR AddcCqR SubbRR SubbCqR

						"Three address ops for RISCs; feel free to add and extend"
						AddCqRR AndCqRR OrCqRR AddRRR SubRRR ArithmeticShiftRightCqRR LogicalShiftLeftCqRR LogicalShiftRightCqRR

						CmpRdRd AddRdRd SubRdRd MulRdRd DivRdRd SqrtRd XorRdRd
						CmpRsRs AddRsRs SubRsRs MulRsRs DivRsRs SqrtRs XorRsRs

						"Conversion"
						ConvertRRd ConvertRdR
						ConvertRsRd ConvertRdRs ConvertRsR ConvertRRs

						SignExtend8RR SignExtend16RR SignExtend32RR
						ZeroExtend8RR ZeroExtend16RR ZeroExtend32RR

						"Advanced bit manipulation (aritmetic)"
						ClzRR
						
						LastRTLCode).

	"Magic auto declaration. Add to the classPool any new variables and nuke any obsolete ones, and assign values"
	"Find the variables directly referenced by this method"
	refs := (thisContext method literals select: [:l| l isVariableBinding and: [classPool includesKey: l key]]) collect:
				[:ea| ea key].
	"Move to Undeclared any opcodes in classPool not in opcodes or this method."
	(classPool keys reject: [:k| (opcodeNames includes: k) or: [refs includes: k]]) do:
		[:k|
		Undeclared declare: k from: classPool].
	"Declare as class variables and number elements of opcodeArray above"
	opcodeNames withIndexDo:
		[:classVarName :value|
		self classPool
			declare: classVarName from: Undeclared;
			at: classVarName put: value].

	"For CogAbstractInstruction>>isJump etc..."
	FirstJump := JumpFull.
	LastJump := JumpFPUnordered.
	FirstShortJump := Jump.

	"And now initialize the backends; they add their own opcodes and hence these must be reinitialized."
	(Smalltalk classNamed: #CogAbstractInstruction) ifNotNil:
		[:cogAbstractInstruction| cogAbstractInstruction allSubclasses do: [:sc| sc initialize]]! !

!Boolean methodsFor: '*VMMaker-breakpoints' stamp: 'eem 12/24/2015 13:01'!
removeBreakpoint: address
	^nil! !

CogRTLOpcodes initialize.
!